Memory controllers are commonly used in a variety of types of computing devices to control how information is accessed from multiple nonvolatile memory devices located within the computing device. In order to communicate with nonvolatile memory devices, existing memory controllers typically employ both a shared bus and a plurality of control lines. Existing memory controllers use the shared bus for transmitting data, address, and control communications to the nonvolatile memory devices connected to the shared bus. Existing memory controllers typically also include multiple pins, or “Chip Selects (CS),” which connect to the control lines. Each control line connects to one of the nonvolatile memory devices. Thus, in order to communicate with a particular nonvolatile memory device, the memory controller typically transmits the data, address, and/or control information on the shared bus, while also enabling the Chip Select corresponding to the target nonvolatile memory device.
Existing memory controllers for controlling nonvolatile memory devices typically suffer from several disadvantages. For instance, existing memory controllers may only support serial communication with the nonvolatile memory devices, which provides slow access to the information contained on the nonvolatile memory devices. In order to receive information from two nonvolatile memory devices, the memory controller first enables the Chip Select for the first device and then transmit an appropriate command on the shared bus and wait for a response to be received via the shared bus. Then, the memory controller may enable the Chip Select for the second device and transmit the command on the shared bus and wait for a response. Obviously, this serial communication scheme may be slow and may be problematic.
Furthermore, existing memory controllers cannot expand beyond the total number of Chip Selects as defined and implemented during the design process. In other words, the number of Chip Selects on a memory controller determines the maximum number of nonvolatile memory devices with which the memory controller may communicate. Thus, the cost of existing memory controllers increases depending on the maximum number of nonvolatile memory devices with which the memory controller is designed to communicate. This tradeoff between expandability and cost may be very problematic in manufacturing memory controllers for nonvolatile memory devices.